System

Chipsets
Early interfaces

The CPU interface is important to the operation of the CPU. It is the physical connection between the processor and the motherboard. As processors improve, so do the CPU interfaces. More pins may be added to the interface to support the advanced features of the processor, or pins may be removed for simplicity when they are no longer needed.

Very First Interfaces
The very first processors didn't use a real interface, they were physically connected to the motherboard and unmovable from their position. There became a need for upgrading of processors, and without an interface, this required the unsoldering and then resoldering of the processor from the mainboard. Chips as early as the 486 started to use a socket interface to connect the chips to the main board. This meant that the chips pins no longer needed to be soldered to the mainboard, instead they could be easily fit into a snug plastic Zero Insertion Force (ZIF) interface that would allow them to be easily removed or replaced at will.

The older chipsets are no longer used because they were only made to support specific processors. Below is a small chart to aid in identification and comparison.

Interface	Supported CPU(s)	Pins
Socket 1	i486	169
Socket 2	i486, Pentium Overdrive	238
Socket 3	i486, Pentium Overdrive, AMD 5x86	237
Socket 4	Pentium 60, 66, and Overdrive	273
Socket 5	Pentium 75 to 133MHz	320
Socket 6	All 486 processors	235

Chipsets
Chipsets are in charge of making the computer work. System features are limited more by the chipset used then be what processor is plugged into the board. Chipsets are in charge of memory address translating, request buffering and queuing, data bus control, frequency timing, and protocol translations - just to name a few. Since the processor isn't capable of handling these tasks, newer future processors like AMD's K8/Sledghammer chip will be designed with an integrated chipset so that it has more control over the rest of the system operations. An integrated chipset would allows for faster performance because it totally eliminates a device, but would make the processor overly complex and large in size Having a chipset integrated into the processor requires advanced production technology and a very small processor fabrication size.

Introduction and Processor Support
This was first introduced in 1995 with the Pentium processor. It is equipped with 296 pins, and supports the Pentium, Pentium MMX, K5, K6, and Cyrix M1.

Features
The Socket 7 interface featured support for motherboard L2 cache which operated at system bus frequency. This was a major downside for the Socket7 interface, because this low-speed cache was a major bottleneck for system performance.

The Sockt7 interface was equipped with a PCI only chipset with up to 512k of L2 cache on the motherboard, which shared memory bandwidth on the 66MHz front side bus. The FSB was later able to operate at the unofficial and unsupported 75MHz and 83MHz bus speeds. It was up to the end user to modify and use these settings, because they would run the system out of specification.

Introduction and Processor Support
This was first introduced in 1997 by AMD for use with their K6-2, K6-3, K6-2+ processors. It was AMD's response to not being able to license Intel's Slot1 interface. Other companies also used this chipset with their chips, like for the Cyrix M2, 6x86, and the IDT Winchip processors. This interface used the exact same 296 pin socket as the original Socket7 interface, but improved on it with more advanced features.

Features
Along with greater processor support, the chipsets were designed with a AGP interface, and improvement over the PCI only Socket7. Depending on the chipset, a 100MHz system bus and up to 2MB of L2 cache could be used. The cache was still on the motherboard via the FSB so performance was still limited. The super7 interface was never able to support multiple processor configurations. Ultra DMA was a standard feature on all of these chipsets.

Chipsets
Because this interface was designed without Intel's help, there were never any Super Socket7 chipsets made by Intel.

	RAM	Cacheable		RAM Types	Cache	Bus Speeds	AGP
ALi Aladdin V	1GB		1GB	EDO,SD	1MB	66MHz, 75MHz, 83MHz, 100MHz	2X
SiS 5591/95	768MB		768MB	EDO,SD	1MB	66MHz, 75MHz, 83MHz, 100MHz	2X
Via Apollo VP2/97	512MB		512MB	EDO,SD	2MB	66MHz, 75MHz, 83MHz	No
Via Apollo VP3	1GB		1GB	EDO,SD	2MB	66MHz, 75MHz, 83MHz	2X
Via Apollo MVP3	1GB		1GB	EDO,SD	2MB	66MHz, 75MHz, 83MHz, 100MHz	2X
Via Apollo MVP4	1GB		1GB	EDO,SD	2MB	66MHz, 75MHz, 83MHz, 95MHz, 100MHz	2X

Socket 8

Introduction and Processor Support
This chipset was only used ever used with Intel processors, namely the Pentium pro and Pentium 3 overdrive.

Features
This interface was a 387 pin socket, and only was used in high end computers. This interface was able to support multiple processor configurations. The L2 cache was taken off of the FSB and on a backside bus where it could operate at full processor frequency. L2 cache was never integrated on the processor die, but imbedded in a special cavity in the processor which allowed it to operate at high speeds, and but still support capacities up to 1MB.

Chipsets
Intel was the only processor manufacturer to use the Socket8 interface, so Intel was responsible for making their own chipsets. Socket8 never got any of the newer features such as AGP or UDMA, and it only was used with the extremely expensive Pentium Pro chips, so it was quickly replaced. All Socket 8 processors operated on a 66MHz bus speed.

	RAM	RAM Types		# CPU
Intel 440FX	1GB		EDO	2
Intel 450GX	1GB		EDO	2
Intel 450KX	4GB		EDO	4
Via VT82C680 Apollo 6	1GB		EDO,SD	4

Slot 1

Introduction and Processor Support
This was introduced by Intel in 1997 for use with its Pentium II, Pentium 3, and celeron. The Slot 1 interface was only used by Intel chips because Intel never sold the rights to any other company. This forced the other processor manufacturers to think of other solutions. This was the main reason why AMD was forced to create the Super Socket7 interface.

Features
It features 242 connections in a slot pattern, which is known as the SC242 connector. The slot design was to allow the processor to be inserted as part of a cartridge, called a Single Edge Contact Cartridge, or SECC for short. Although this increased manufacturing costs, the SECC was able to hold L2 cache, up to 512k. This was a good design because it allowed the L2 cache to reside off of the motherboard, like how it was with the Socket7 interface. This meant that like the Socket8 interface, the L2 cache could be situated on a backside bus, with dedicated bandwidth to the CPU. Unlike the Pentium Pro, the L2 cache was not able to operate at full processor speed, because it was too far from the processor. Once manufacturing processes improved and L2 cache was able to be made on-die, the Slot 1 interface was slowly replaced to save money.

Chipsets
The slot 1 interface was able to support up to 2 processors with a compatible chipset. All chipsets used with the Slot 1 interface are also compatible with

Click HERE to for an enlarged version

Slot 2 was introduced by Intel in 1998 for exclusive use with their Xeon processors. The slot uses the 330 pin SC330 connector, which adds extra pins which become useful for multiprocessor support. The Slot2 interface can be used in 2, 4 or 8 way processor systems.

The Pentium II Xeon and Pentium 3 xeons are made with a SECC2 format. The SECC2 and Slot2 interface are very large, because of the size the PCB needs to be. Xeon processors use up to 2MB of L2 cache, which is large in size and needs a large area to be placed. The Slot2 interface is only used in high end server systems, and is very expensive.

	RAM	Bus Speed	AGP	# of CPU
Intel 440GX	2GB	100MHz	2X	2
Intel 450NX	8GB	100MHz	no	4

Introduction and Processor Support
The Socket 370 is capable of supporting all socket versions of Intel's Celeron, Celeron II, and Pentium III, as well as VIA's Cyrix III. It was first introduced in April of 1999 to reduce costs that are associated with the SECC packaging that all slot chips require. The onboard L2 cache that all newer chips had would make the packaging a complete waste, so the Socket interface soon returned as the most economical solution.

There are two versions of the Socket370 interface, the early version that was only able to support PPGA socket processors, and the newer version that supports both the PPGA and FCPGA processors. Both interfaces use the identical 370 interface, the only difference lies in the way the processor is manufactured. Flip Chip Grid Pin Array processors are inverted in the interface with the die on top of its host substrate, as opposed to underneath like the PPGA format. This reverses the pins, making it incompatible to some older motherboards. Socket370 was designed to be the economical solution, but because of Slot1 chipset compatibility, it is widely used for even the highest performance chips. The Socket 370 interface uses the same chipsets as the Slot 1 interface.

Introduction and Processor Support
This interface was developed by AMD in July of 1999 for exclusive use with their Athlon processors. AMD was forced to develop their own interface for use with their next generation processor because Intel was reluctant to license either their Slot1 or Socket370 interface. AMD needed a high performance interface to replace the severely limited Super Socket7 interface. The SlotA uses the same 242 pin SC242 connector, making the interface physically compatible with Slot1 but electrically incompatible and the use of Intel processors impossible.

Features
AMD needed a high performance chipset, so it licensed the EV-6 bus from Digital Equipment Corporations, and this was a major improvement over FSB protocol Intel uses. It allows the first AMD processors to operate on a 100MHz DDR, effectively 200MHz, bus, which was twice as fast as the early Intel chips. SlotA was never able to operate with multiprocessor support because the chipsets were never allowed to evolve enough before being replaced by SocketA.

Chipsets
There were only 2 chipsets ever used with the SlotA interface, one from AMD, and a newer and improved chipset by VIA. Both operate with a 100MHz DDR FSB, ATA66 and only SD RAM.

Chipset	Memory Types	Maximum Memory	AGP	Chipset-FSB Timing
AMD 750	100MHz	768MB	2X	Synchronous
VIA KX133	100-133MHz	2GB	4X	Asynchronous

Socket A

Introduction and Processor Support
AMD has quickly replaced the SlotA interface with the SocketA interface. By using a socket interface for the CPU, the costly slot packaging can be removed, and the CPU can be closer to the chipset allowing for faster FSB speeds. The SocketA interface uses 462 pins and the same 100MHz DDR EV-6 bus as the slot form. This interface is used for only AMD's second generation Athlon, code named Thunderbird, and AMD's Duron processors, because unlike the first generation Athlon, they feature on-die L2 cache, which makes the socket interface possible.

Features
There haven't been any new features which have been added to the current SocketA chipsets over the SlotA interfaces, except allowing for ATA100.

Chipsets
There is currently (August 2000) only one chipset available for the SlotA format, which is VIA's KT133. It is basically the same chipset as the SlotA's KX133, except with a few minor modifications to ensure compatibility. Future chipsets are planned by companies; such as AMD, VIA, and Acer Laboratories (ALi); to be released soon with added that will allow ATA100, DDR DRAM, and multiprocessor configurations.

Chipset	Memory	FSB	# of CPU's
KT133	100, 133MHz	100MHz DDR	1
AMD 760	PC2100	133MHz DDR	1
AMD 760MP	PC2100	133MHz DDR	1-2
VIA K7-DDR	PC2100	133MHz DDR	1
ALiMAGiK 1	PC2100	100MHz DDR	1
RED TEXT denotes unreleased chipsets

A bus is a highspeed path in which data travels. It can be thought of as a pipe. The water which travels through this pipe is called data. It is a string of binary information that is needed at the other end of the pipe. The width and size of this pipe is the number of bits that can be transferred at a time. The overall amount of data that can be transferred per second is called bandwidth. Most high speed buses have 32-bit widths, and with some having even more. The advantages of a wide width is that a lot of data can flow through it at once. The downside, which is often the limit for the bus width, is the physical size which a bus has. The water pressure in the pipe would be the frequency. Even a small bus width is capable of high bandwidth, if its frequency is high enough.

Industry Standard Architecture

ISA was released with the first IBM PC. The oldest implementation was as a 8-bit bus running at 4.77MHz. ISA went through a couple upgrades, first up to 16-bits. A few speed increases, 6MHz up to 8MHz, and again up to 8.33MHz. ISA is still used today in systems for legacy support for older devices, although it is on its last leg.

A final advancement was made to the ISA bus, it was increased to be 32-bits wide and operating at the same at the same 8.33MHz frequency. This was to ensure backwards compatibility with old ISA devices. EISA was developed around the same time as the MCA by Compaq as a high bandwidth solution to the aging and slow ISA. It featured double the bandwidth of the ISA bus, and nearly that of the MCA, IRQ sharing and a basic implementation of plug-and-play. EISA was a great step in the right direction, but because it suffered from numerous technical problems it was never looked at as a practical solution.

Introduced by IBM, MCA was a 32-bit with plug and play and bus master architecture. It was used only in IBM PS/2 systems, and few other companies because IBM was a forcing other companies to pay a royalty to use it. The MCA was introduced around the same time as EISA, but neither formats were ever used extensively in the computer industry.

VL-Bus was a new technology that instead of communicating to the CPU through the core logic chipset like the other buses, VL-Bus tapped directly into the front side bus. This was a very strict standard because devices had to be very well behaved. There was no longer a chipset to moderate the devices. Although directly connecting devices to the CPU proved to be a fast bus, it would place a lot of strain on the CPU by creating electrical issues. This limited the performance at which the bus could run, and also limited the number of VL-Bus devices in a system to two. The speed of this bus was the same as the front side bus, so in most 486's that meant a 32-bit 33MHz bus. VL-Bus cards plugged into the motherboard through regular ISA slots, but had a special connector which was plugged into a special connection on the motherboard so that the card could gain access to the FSB.

The PCI bus was introduced by Intel in 1992 as a replacement to the VL-Bus. Instead of connecting components directly to the FSB like the VL-Bus, the PCI bus used a special connection through the northbridge, which still allowed them dedicated access to the CPU and main memory. The PCI bus is faster than the VB-Bus, and suffered none of the electrical problems that plagued the VL-Bus. These factors made the PCI bus catch on rather quickly, and it is still used today in all x86 systems.

PCI 2.0
At introduction, the PCI bus operated at a 32-bit 33MHz bus, just like the VL-Bus, except now the FSB operated at twice that speed, 66MHz.

PCI 2.1
PCI 2.1 specification is for a 66MHz 32-bit bus. This doubles the effective speed of the bus, but takes limited hardware modifications to achieve. Many older video cards were sold for this format, but this later evolved into AGP.

PCI 2.2
PCI 2.1 specification calls for a 66MHz 64-bit bus. This is used in high end servers for connections like Fibre Channel, SCSI, or Ethernet.

Because the PCI bus is limited to approximately 127MB/sec for all devices, there was a need for a faster bus for use by the video card. Unlike hard drives or sound cards, video cards have to make frequent accesses to main memory, along with large texture transfers. The AGP specification was only for a dedicated 66MHz PCI bus for the video card, and was very similar to the PCI2.1 specification. Along with extra speed and dedicated memory access, AGP had more beneficial features. These included AGP texturing, sidebanding, write combining, and fast writes.

AGP texturing
This is a faster form of PCI texture prefetching. It would access the needed textures from memory instead of the onboard video RAM. This is often to slow to work well, even with the AGP's dedicated access and AGP4X.

The original AGP interface only operated as a 32-bit 66MHz bus. It was quickly revised into a 32-bit 133MHz which was capable of 2 complete transfers per clock. This was called AGP2X because it was 2X as fast as the original. This raised the bandwidth from the AGP's 254MB/sec to 508MB/sec. If this wasn't enough, the bus has been expanded to make use of 4 complete transfers per clock in a AGP4X specification. The bus now operates as a 32-bit 266MHz bus with bandwidth up to 1007MB/sec. Most newer computers are using the AGP4X format, but the AGP2X is still very common.

Sidebanding
This is the process which overlaps requests from the video card to the northbridge. This can provide a speed increase, but is know to cause problems with some video cards.

Write combining
This is the practice that allows the merger of multiple requests or operations into a single read or write, fully taking advantage of AGP's extra bandwidth. This is a significant speed increase, and unlike sidebanding and fast writes, it will not cause problems with the video card stability.

Fast Writes
This is where the CPU is allowed to make requests directly to the AGP card rather than put it in the video card's buffer. Fast writes are not supported by all cards, and are know to cause severe stability problems with some configurations. They also offer only small performance gains, and can be used only in specific situations. Therefore this feature is rarely implemented.

This architecture is used with Rambus enabled motherboards. Instead of a northbridge and a southbridge, there are 2 hubs which operate in the same manner. The only difference is that instead of connecting the two by using a 8-bit high speed bus operating at 133MHz. This allows the Rambus to effectively transfer its information from one of its channels, while simultaneously transferring to another bus through the north hub.

We all know and love decimals. Decimals run on a base 10 system. There are 10 numbers in each unit holder. Computers operate on binary signals, 0's for off, and 1's for on. This is base 2, because each column has 2 possible values. For large numbers, binary can get hard to read so low level computer language is presented in Hexadecimal. Hexadecimal is base 16 because each column contains 16 different possible values. There are the 10 values, 0 through 9, and the letters A, B, C, D, E, and F.

ASCII codes is short form for American Standard Code for Information Interchange. This standard was made to develop a common way of presentation in early computers. Each ASCII code uses 7-bits, making 127 different characters. This was later changed to 256 characters with the inclusion of the extended ASCII codes, for the purpose of using complete bytes for characters. The extended ASCII codes were used by early computers that were only capable of alphanumerical block display, and not capable of per pixel addressing. Extended ASCII codes were made to include useful characters that could be used to create borders and lines. There are many different versions of extended ASCII code, but all serve the same purpose. Extended ASCII codes do not serve the same usefulness to todays computers as they did a while ago, so support for extended ASCII in newer computers is selective. 7-bit ASCII is still very popular because of its small storage size, and low level functionality.

Dec Hx Char                     Dec Hx Char Dec Hx Char  Dec Hx Char
---------------                 ----------- -----------  -----------
  0  0 NUL (null)                32 20 SPACE 64 40 @      96 60 `
  1  1 SOH (start of heading)    33 21 !     65 41 A      97 61 a
  2  2 STX (start of text)       34 22 "     66 42 B      98 62 b
  3  3 ETX (end of text)         35 23 #     67 43 C      99 63 c
  4  4 EOT (end of transmission) 36 24 $     68 44 D     100 64 d
  5  5 ENQ (enquiry)             37 25 %     69 45 E     101 65 e
  6  6 ACK (acknowledge)         38 26 &     70 46 F     102 66 f
  7  7 BEL (bell)                39 27 '     71 47 G     103 67 g
  8  8 BS  (backspace)           40 28 (     72 48 H     104 68 h
  9  9 TAB (horizontal tab)      41 29 )     73 49 I     105 69 i
 10  A LF  (NL line feed)        42 2A *     74 4A J     106 6A j
 11  B VT  (vertical tab)        43 2B +     75 4B K     107 6B k
 12  C FF  (NP form feed)        44 2C ,     76 4C L     108 6C l
 13  D CR  (carriage return)     45 2D -     77 4D M     109 6D m
 14  E SO  (shift out)           46 2E .     78 4E N     110 6E n
 15  F SI  (shift in)            47 2F /     79 4F O     111 6F o
 16 10 DLE (data link escape)    48 30 0     80 50 P     112 70 p
 17 11 DC1 (device control 1)    49 31 1     81 51 Q     113 71 q
 18 12 DC2 (device control 2)    50 32 2     82 52 R     114 72 r
 19 13 DC3 (device control 3)    51 33 3     83 53 S     115 73 s
 20 14 DC4 (device control 4)    52 34 4     84 54 T     116 74 t
 21 15 NAK (negative acknowledge)53 35 5     85 55 U     117 75 u
 22 16 SYN (synchronous idle)    54 36 6     86 56 V     118 76 v
 23 17 ETB (end of trans. block) 55 37 7     87 57 W     119 77 w
 24 18 CAN (cancel)              56 38 8     88 58 X     120 78 x
 25 19 EM  (end of medium)       57 39 9     89 59 Y     121 79 y
 26 1A SUB (substitute)          58 3A :     90 5A Z     122 7A z
 27 1B ESC (escape)              59 3B ;     91 5B [     123 7B {
 28 1C FS  (file separator)      60 3C <     92 5C \     124 7C |
 29 1D GS  (group separator)     61 3D =     93 5D ]     125 7D }
 30 1E RS  (record separator)    62 3E >     94 5E ^     126 7E ~
 31 1F US  (unit separator)      63 3F ?     95 5F _     127 7F DEL

Most keyboards are able to produce ASCII symbols by holding down the "ALT" key, while using the "keypad" numbers to input the ASCII value. On release of the "ALT" key, an ASCII value is produced.

A core logic chipset is the nervous system of a computer. The Central Processing Unit is more like the brain. The CPU is responsible for all of the "thinking" but the chipset is responsible for allowing everything to communicate.

Translating

The core logic chipset is basically responsible for the CPU's dirty work. When the CPU sends a memory address for a read, the core logic chipset's job is to find where the memory location is, whether it is in main memory, on the hard drive, or on a peripheral like a video card or serial port. Next, it relays the request in a form which the device can understand. This translation will take 1 clock cycle on most computers. The translation will take up to one cycle for the chipset to process, and if the FSB and System Bus run asynchronously, then another cycle is often needed to correctly time the signals.

One of the many tasks that a chipset has is to provide a way for the CPU to communicate with main memory.

One of the major tasks in memory access is memory support. The core logic chipset is responsible for all of the addressing of memory locations. Remember that the CPU sees memory as a linear storage line. Memory is actually a complex network of 2 dimensional arrays of information which is interleaved between multiple chips on a separate modules. The chipset translates the linear addressing of the CPU to the multiple bank spanning single bit storage method that memory uses.

This means the chipset is also responsible for supporting the different features that different DRAM have, such as Fast Page Mode DRAM's ability to burst consecutive CAS cells without having to resend the RAS address, and Synchronous DRAM's ability to have multiple banks and ability to incremental burst without needing to be sent either RAS or CAS lines. This is not to mention the advanced functions that RDRAM use.

CPU clockspeed is determined by the bus frequency which it is connected to. Because most bus frequencies only are able to operate at speeds up to 133MHz, a multiplier is used. Multipliers and bus frequencies are all generated by a special chip, called a frequency generator. This chip is responsible for the timing of all of the chips on the motherboard, including the CPU. This chip produces a special signal which is referenced by specific devices so that the devices know how fast to operate. All CPU, AGP bus, memory bus, PCI bus, and internal chip operation is controlled by these signals. For simplicity, clock generators are able to operate with multipliers in 0.5 increments. Most motherboards are capable of supporting multipliers from 5.5 all of the way up to 8.5. These multiplier settings are used by the CPU in conjunction with the CPU's bus frequency. If a CPU is operating on a 100MHz bus, and it has a 6.5 multiplier, the chip knows to operate at 650MHz.

This is the information pathway between the CPU and the core logic chipset. Normally there is nothing else connected on this bus, although some older 486's used a VL-Bus connection, which proved to be unstable and limiting to FSB operations.

Most consumer computers use an operating system made by Microsoft. This is the reason, Bill Gates, the owner of Microsoft is the worlds richest man.

Disk Operating System (DOS)
DOS was one of the very first operating systems. It was a command line based operating system (CLI), although it did allow some primitive GUI's to run overtop of it. It was still widely used up to about a year ago, with major game titles such a Tomb Raider, being programmed for it. For legacy support, Windows 3.1, Windows 95, Windows 98, and Windows Millenium all operate out of DOS.

Windows 3.1
This was the first step of the GUI. It was horribly implemented, and still relied on console commands to perform most major operations.

Windows 95
This was the king of it's day. It made the total conversion to the GUI, and made console commands obsolete. These radical changes took there toll, and made this OS one of the most unstable and frustrating OS ever made.

Windows98
This was built based on the Win95 OS, with major tweaks in customizability, user-friendliness, and stability. It thrived to integrate a web browser into the core OS, which at first was not thought of as a good idea. This is currently the most used OS, and for good reason. It is friendly, optimized for gaming performance, and is compatible with almost every piece of hardware and software imaginable, plus it is fairly stable.

WindowsNT
This was Microsoft's first attempt at a server OS. It was plagued with security flaws, and wasn't capable of being the OS that was needed to be. This was also the first Microsoft OS to remove DOS compatibility, which, while giving it a performance boost it also took away all of the hardware and software compatibility that Windows98 had.

Windows2000
Windows2000 is currently the OS used by many high end computers. It has all of the compatibility of Windows98, and all of the performance and stability of WindowsNT.

The Windows registry is where all of the user settings for programs are stored. Did you ever wonder how Windows remembers how you arranged your desktop icons yesterday, or what documents you viewed? It is all stored in the registry. The registry is broken up into 2 files, system.dat and user.dat in the Windows folder. These files are editable with a program called Regedit.exe located in your Windows folder. But editing the registry is not for the inexperienced, a single mistake could mean your computer won't boot next time you power it on.

OS's like Windows98 or greater allow an automated registry backup every day, so if you do make a mistake, at least you have something to fall back on. One thing to remember, all registry changes are immediate, and there is no undo command.

There are 2 ways of getting information to the computer, Polling and interrupts.

Polling
The first way is called polling. This involves the device to check all of it's connections to see if there is data waiting. This is very inefficient because processing time is wasted while the CPU has to poll the different devices. This is also a waste because there may not even be any data waiting for the CPU. If polling isn't performed often enough, then urgent data could be waiting until the connection is polled. On the other had, if there is no data, then polling too often will cause a major performance hit. Polling is a very simple way of getting information, and for this reason it is used on low bandwidth and low urgency devices such as mice and keyboards. This polling isn't done by the CPU, mind you, it is performed by a dedicated I/O Controller, which in turn has an IRQ to the CPU.

Interrupts
Interrupt Requests (IRQ's) are more efficient than polling because they interrupt the processor only when they need CPU attention. Each device is attached to an Interrupt Request Line. The device sends a signal to the processor through the IRQ line, and the CPU only has poll the device when there is a request in its IRQ buffer. This is very quick and efficient. When the processor has time, it contacts that device which made the interrupt and requests the data.

The first computers had only 8 interrupts, number 0 to 7. This proved to be too few, but in order to maintain compatible, a second interrupt controller was "cascaded" from the first using the 2nd IRQ. The 2nd interrupt was then remapped to the 9th IRQ. This almost doubled the amount of IRQ's available to the system. This proved to be enough, for a while.

Before plug-and-play, device IRQ's had to be set up manually. IRQ's are assigned during boot time, establishing links to the devices. IRQ's can be changed manually in the BIOS, or the BIOS can assign them if the devices are plug and play. To prevent the end user from having to rearrange IRQ's every time a device was added, manufacturers started to use a set pattern for which devices used which IRQ's.

As you can see, there aren't many free interrupts, and most devices need their own. To solve the problem of limited IRQ's, IRQ Sharing was developed and released in Windows95 Service Release 2. This is where two devices can share the same IRQ. Only certain devices can do this, because if both devices need the IRQ at the same time, problems can arise.

IRQ	Commonly Used For
0	System Timer
1	Keyboard
2	2nd IRQ Controller
3	Serial Port (COM2)
4	Serial Port (COM1)
5	2nd Parallel-Port (LPT2) or NIC
6	Floppy Disk
7	Parallel Port (LPT)
8	Real Time Clock
9	(free)
10	Soundcard or NIC
11	(free)
12	PS-2 Mouse
13	FPU Math Co-Processor
14	Primary IDE Controller
15	Primary IDE Controller

IRQ Steering
IRQ Steering only works with PCI bus devices. IRQ Steering is a more advanced plug-and-play, and is also used to remap IRQs during run time for IRQ sharing. It will not work with ISA devices because they all require their own dedicated IRQ. IRQ Steering, which is also referred to as PCI bus IRQ steering, works by having operating system assign IRQ's instead of the BIOS. Windows displays a "IRQ Holder for PCI Steering" in the "System Device" listing if IRQ Steering is being used on a device. For IRQ sharing, the OS monitors the IRQs and devices, and remaps the IRQ to the device which needs to use it.

I/O Controller
The I/O controller is responsible for monitoring devices when they have information that needs to be transferred. This controller will schedule the interrupts for different devices and make sure that the device is ready so that data transfers can go smoothly and without hiccup.

Standard DMA
DMA allows devices to directly access memory without the need to channel their requests through the processor. By directly accessing memory, they allow the processor to carry on uninterrupted at its task.

DMA is achieved by having a device send a special request to the DMA controller. The DMA controller, in turn will send another signal to the CPU, indicating that a device wants to access memory. This signal is known as a Bus Request signal. The CPU will then close all I/O requests, and clear the address bus and data bus. It will then notify the DMA controller that it is free to use the bus. The DMA controller will act like a basic secondary CPU, and process the device's memory requests.

During this state, no other device is allowed to use either the address bus, or the data bus, including the CPU. The device and DMA controller have complete access to it - this is called bus mastering. The device is able to burst information over the bus because it is free from interrupts, which is one of the reasons why DMA offers improved transfer speed over PIO transfers.

When the memory access is complete, the DMA controller frees the address bus and data bus, and then notifies the CPU that it may resume normal control. During bus mastering, the CPU is continuing on with its processing with the information which is stored in its cache. Because the CPU will eventually need more information after a few clock cycles, bus mastering was never designed to last any significant length of time.

There are 8 DMA buses in all systems, and each of these buses can be used by only one device each. Devices that use DMA are assigned which channel to use during boot time.

DMA	Common Device
0	(free)
1	(free)
2	Floppy Drive
3	Parallel Port
4	DMA Controller
5	Legacy Sound Card
6	(free)
7	(free)

The Direct Memory Access controller acts like a second CPU which is dedicated to moderating the memory access. Instead of channeling requests through the CPU, DMA devices send their requests through their dedicated DMA channel to the DMA controller.

Ultra DMA
Ultra DMA is an improvement over DMA in that it no longer uses DMA channels for memory access by DMA devices. Each UDMA device can act as its own DMA controller, and perform all the necessary operations to control the data bus.